1. Field of the Invention
This invention relates to a test simplifying circuit in a large-scale digital system, and more particularly to a test simplifying circuit for permitting self testing of a large-scale integrated circuit.
2. Description of the Related Art
A scan test method is known as a conventional technique for simplifying testing of a large-scale digital system. The scan test method is effected by use of a circuit shown in FIG. 1. That is, a plurality of memory elements 81 provided in a synchronous digital circuit are connected in a shift register configuration when a test is effected. Serial data SI is sequentially supplied to the memory elements 81. As a result, desired values are set into the respective memory elements 81, and the values set in the memory elements 81 and external input data PI are supplied to a random circuit (combinational circuit) 82. The test is effected by storing data other than PO which is external output data among the output signals of the random circuit 82 into the memory elements 81 again and reading out the data as serial data SO in a serial manner.
That is, in this scan test method, it is possible to deal with data input and output lines to the internal memory elements as imaginary external input/output terminals. As a result, the entire circuit can be dealt with as an imaginary combinational circuit.
A test data automatic generation method capable of detecting defects in the combinational circuit with a fault detection rate of 100% is known in the art. Therefore, it becomes possible to automatically generate test data in a digital system in which data can be scanned.
However, in this scan test method, serial data must be supplied when the test is effected. Therefore, when the circuit is formed on a large scale, an expensive testing device is used and the test period becomes a problem. Further, the scan test method cannot comply with the self-test which is the most ideal scan test at present.
Further, a compact test method for enabling the self-test is the conventional technique. The compact test method is effected by using the circuit shown in FIG. 2. That is, the test method is effected by supplying a test pattern created by a random pattern generation circuit 84 to a digital system 83 to be tested, compressing a response output generated at this time from the to-be-tested object by means of a data compactor 85, and comparing the same with a signature read out from a signature storing section 86, and indicating the final state of the compactor by use of using a comparator 87 to determine whether the to-be-tested digital system 83 is normal or not. In general, a linear feedback shift register, which is hereinafter referred to as LFSR, is used in each of the random pattern generator 84 and the data compactor 85. In a case where the random pattern generator, data compactor, and signature comparing means are formed in an integrated circuit, this method has a feature that the self-test of the integrated circuit can be effected. However, In this method, since a random pattern is supplied to the to-be-tested object, the following problem occurs. That is, even when a large amount of random patterns are supplied to a general sequential circuit, the fault detection rate may not be raised in some cases.
In this case, a generation pattern must be created according to the circuit-signature of the digital system to be tested. Further, in the case of the sequential circuit, care must be taken to the timings at which patterns are supplied. Therefore, when a random pattern is supplied, the timing specification of the digital system to be tested must be satisfied. The above two problems are serious problems when the compact test method is applied to a general digital system and make the design of a test simplifying circuit complicated.
Further, in this method, it is possible to determine whether the to-be-tested object is effective or not, but it cannot comply with the case wherein an analysis such as identification of the fault position must be effected.
A boundary scan test method is known as another conventional test method. This method is effected by use of the circuit shown in FIG. 3. In this test method, storage elements 92 are provided for respective input/output signals corresponding to boundary portions of logic circuits 91 to be tested. The method is used to simplify the test by reconstructing them to perform the shift operation when the test operation is effected. In a case where a test pattern having a fixed fault detection rate for a specified logic circuit is prepared, the test for the logic circuit to be tested can be effected by applying the pattern to the boundary portion of the boundary scan in a sequential manner and observing the same. Further, a test for wirings (external wirings) between individual logic circuits having the boundary scan function added can be effected by use of the same circuit. This method has the above described advantages, but at the same time it has the following problems. In a case where no test pattern for testing the individual logic circuits is present, the value of the circuit as the test simplifying circuit is reduced. Further, like the compact test method, special care must be taken into consideration when a digital circuit to be tested in the boundary scan is a sequential circuit and if it is necessary to pay attention to the relationship between timings of application of the test patterns.
Thus, conventionally, the scan method, compact test method, boundary scan method and the like are provided as a test technique for systematically simplifying the test for large-scale digital systems. However, they have individual problems as described above.